Intel focuses on energy efficiency in at ISSCC conference

At this year’s International Solid State Circuits Conference (ISSCC), which is held from February 9 to 13, Intel is presenting multiple papers addressing energy efficiency, an increasingly critical consideration for engineers designing everything from smartphones to supercomputers. 

Source: Intel. This wafer contains efficient network-on-chip circuits scalable to hundreds of compute nodes. The circuits enable the industry's first 256-node network-on-chip in 22nm Tri-Gate CMOS* that operates at near-threshold and ultra-low-voltage, decreasing power by 9x to 363μW at 340mV. An Intel paper on this topic was presented at ISSCC (paper 16.1).

This includes a paper about a graphics execution core that achieves 40% higher peak energy efficiency, a 10x reduction in sleep-state power and 2.7X higher gigaflops per watt at near-threshold voltage. Another paper demonstrates platform input/output circuits and interconnects with industry-leading energy efficiency and scalable performance. 

While these are research papers, the work could ultimately lead to energy efficient systems on a chip (SoCs) and platforms with better graphics and enhanced security, says Intel.

*CMOS or complementary metal–oxide semiconductor is a method for constructing computer chips.

*A gigaflop is a billion floating-point operations per second (FLOPS), a measurement for computer performance.