Toshiba starts sampling shipments of BiCS FLASH 3D memory

Source: Toshiba. Toshiba begins sample shipments for new BiCS FLASH 3D 
memory.

Toshiba has begun sample shipments for the latest generation of its BiCS FLASH three-dimensional (3D) flash memory. The chips have a 64-layer stacked cell structure* which incorporates 3-bit-per-cell (triple-level cell, TLC) technology and achieves a 256-gigabit (32-gigabyte) capacity, an advance that underscores the potential of Toshiba’s proprietary architecture.

The new device succeeds the 48-layer BiCS FLASH, and its 64-layer stacking process realises 40% more capacity per unit chip size than the previous 48-layer stacking process. The cost per bit is lower too. The 64-layer BiCS FLASH is expected to be used in applications that include enterprise and consumer solid state drives (SSDs), smartphones, tablets and memory cards.

Toshiba will produce the new 64-layer BiCS FLASH in the New Fab 2 at Yokkaichi, which was officially opened earlier this month. Mass production of the 64-layer BiCS FLASH chips is scheduled to start in the first half of 2017.

The next milestone on the development roadmap is a 512-gigabit (64-gigabyte) device, also with 64 layers.

Interested?

Read the TechTrade Asia blog post about the new Yokkaichi operations

*Basically a skyscraper instead of a single-storey building. A structure stacking flash memory cells vertically on a silicon substrate to realise significant density improvements over planar NAND Flash memory, where cells are formed on the silicon substrate.